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16 megabit flash eeprom dpz512x32iv3 description: the dpz512x32iv3 ??versa-stack?? module is a revolutionary new memory subsystem using dense-pac microsystems? ceramic stackable leadless chip carriers (slcc) mounted on a co-fired ceramic substrate. it offers 16 megabits of flash eeprom in a single package envelope of 1.090" x 1.090" x .470". the dpz512x32iv3 is built with eight slcc packages each containing two 128k x 8 flash memory devices. each slcc is hermetically sealed making the module suitable for commercial, industrial and military applications. by using slccs, the ??versa-stack?? family of modules offers a higher board density of memory than available with conventional through-hole, surface mount, module or hybrid techniques. features: organization: 512k x 32, 1 meg x 16 fast access times (max.): 120, 150, 170, 200, 250ns fully static operation - no clock or refresh required ttl compatible inputs and outputs common data inputs and outputs 10,000 erase/program cycles (min.) 66 - pin pga ??versa-stack?? package pin-out diagram pin names a0 - a16 address inputs i/o0 - i/o31 data input/output ce 0 - ce 7 chip enables we 0, we 1 write enables oe output enable programming v pp voltage (+12.0v) v dd power (+5v) v ss ground n.c. no connect functional block diagram this document contains information on a product that is currently released to production at dense-pac microsystems, inc. dense-pac reserves the right to change products or specifications herein without prior notice. 30a072-12 rev. c 1
dpz512x32iv3 dense-pac microsystems, inc. device operation: the flash devices are electrically erasable and programmable memories that function similarly to an eprom device, but can be erased without being removed from the system and exposed to ultraviolet light. each 128k x 8 device can be erased individually eliminating the need to re-program the entire module when partial code changes are required. read: with v pp = 0v to v dd (v pplo ) , the devices are read-only memories and can be read like a standard eprom. by selecting the device to be read (see truth table and functional block diagram) , the data programmed into the device will appear on the appropriate i/o pins. when v pp = +12.0v 0.6v (v pphi ) , reads can be accomplished in the same manner as described above but must be preceded by writing 00h 1 to the command register prior to reading the device. when v pp is raised to v pphi the contents of the command register default to 00h 1 and remain that way until the command register is altered. standby: when the appropriate ce ?s are raised to a logic-high level, the standby operation disables the flash devices reducing the power consumption substantially. the outputs are placed in a high- impedance state, independent of the oe input. if the module is deselected during programming or erase, the device upon which the operation was being performed will continue to draw active current until the operation is completed. program: the programming and erasing functions are accessed via the command register when high voltage is applied to v pp . the contents of the command register control the functions of the memory device (see command definition table) . the command register is not an addressable memory location. the register stores the address, data, and command information required to execute the command. when v pp = v pplo the command register is reset to 00h 1 returning the device to the read-only mode. the command register is written by enabling the device upon which that the operation is to be performed (see functional block diagram) . while the device is enabled bring we to a logic-low (v il ). the address is latched on the falling edge of we and data is latched on the rising edge of we . programming is initiated by writing 40h 1 (program setup command) to the command register. on the next falling edge of we the address to be programmed will be latched, followed by the data being latched on the rising edge of we (see ac operating and characteristics table) . program verify: the flash devices are programmed one location at a time. each location may be programmed sequentially or at random. following each programming operation, the data written must be verified. to initiate the program-verify mode, c0h 1 must be written to the command register of the device just programmed. the programming operation is terminated on the rising edge of we . the program-verify command is then written to the command register. after the program-verify command is written to the command register, the memory device applies an internally generated margin voltage to the location just written. after waiting 6 m s the data written can be verified by doing a read. if true data is read from the device, the location write was successful and the next location may be programmed. if the device fails to verify, the program/verify operation is repeated up to 25 times. erase: the erase function is a command-only operation and can only be executed while v pp = v pphi . to setup the chip-erase, 20h 1 must be written to the command register. the chip-erase is then executed by once again writing 20h 1 to the command register (see ac operating and characteristics table) . to ensure a reliable erasure, all bits in the device to be erased should be programmed to their charged state (data = 00h) prior to starting the erase operation. with the algorithm provided, this operation should typically take 2 seconds. high performance parallel erasure: dense-pac recommends that all users implement the following intel high performance parallel erase algorithm in order to avoid the possibility of over erasing these parts. in applications containing more than one flash memory, you can erase each device serially or you can reduce total erase time by implementing a parallel erase algorithm. you may save time by erasing all devices at the same time. however, since flash memories may erase at different rates, you must verify each device separately. this can be done in a word-wise fashion with the command register reset command and a special masking algorithm. take for example the case of two-device (parallel) erasure. the cpu first writes the data word erase command 2020h twice in succession. this starts erasure. after 10ms, the cpu writes the data word verify command a0a0h to stop erasure and setup erase verification. if both one or both bytes are not erased at the given address, the cpu implements the erase sequence again without incrementing the address. suppose at the given address only the low byte verifies ffh data? could the whole chip be erased? the answer is yes. rather than check the rest of the low byte addresses independently of the high byte, simply use the reset command to mask the low byte from erasure and erase verification on the next erase loop. in this example the erase command would be 20ffh and the verify command would be a0ffh. once the high byte verifies at the address, the cpu modifies the command back to the default 2020h and a0a0h, increments to the next address, and then writes the verify command. see figure 4 for a conceptual view of the parallel erase flow chart and figure 4 for the detailed version. these flow charts are for the 16-bit systems and can be expanded for 32-bit designs. erase verify: the erase operation erases all locations in the device selected in parallel. upon completion of the erase operation, each location must be verified. this operation is initiated by writing a0h 1 to the command register. the address to be verified must be supplied in order to be latched on the falling edge of we . the memory device internally generates a margin voltage and applies it to the addressed location. if ffh is read from the 30a072-12 rev. c 2
dense-pac microsystems, inc. dpz512x32iv3 device, it indicates the location is erased. the erase/verify command is issued prior to each location verification to latch the address of the location to be verified. this continues until ffh is not read from the device or the last address for the device being erased is read. if ffh is not read from the location being verified, an additional erase operation is performed. verification then resumes from the last location verified. once all locations in the device being erased are verified, the erase operation is complete. the verify operation should now be terminated by writing a valid command such as program set-up to the command register. product i.d. operation: the product i.d. operation outputs the manufacturer code (89h) and the device code (b4h). this allows programming equipment to match the device with the proper erase and programming algorithms. with ce and oe at a logic low level, raising a9 to v id (see dc operating characteristics) will initiate the operation. the manufacturer?s code can then be read from address location 0000h and the device code can be read from address location 0001h. the i.d. codes can also be accessed via the command register. following a write of 90h to the command register, a read from address location 0000h outputs the manufacturer?s code (89h). a read from address location 0001h outputs the device code (b4h). to terminate the operation, it is necessary to write another valid command into the register. power up/down protection: the flash devices are designed to protect against accidental erasure or programming during power transitions. it makes no difference as to which power supply, v pp or v dd, powers up first. power supply sequencing is not required. internal circuitry ensures that the command register is reset to the read mode upon power up. power supply decoupling: v pp traces should use trace widths and layout considerations comparable to that of the v dd power bus. the v pp supply traces should also be decoupled to help decrease voltage spikes. while the memory module has high-frequency, low-inductance decoupling capacitors mounted on the substrate connected to v dd and v ss , it is recommended that a 4.7 m f to 10 m f electrolytic capacitor be placed near the memory module connected across v dd and v ss for bulk storage. decoupling capacitors should also be placed near the module, connected across v pp and v ss . command definition table command bus cycles req?d first bus cycle second bus cycle operation address data 1 operation address data 1 read memory 1 write x 00h - - - setup erase / erase 2 write x 20h write x 20h erase verify 2 write ea a0h read x evd setup program / program 2 write x 40h write pa pd program verify 2 write x c0h read x pvd reset 2 write x ffh write x ffh read product i.d. codes 3 write x 90h read ia id ea = address to verify pa = address to program evd = data read from location ea pd = data to be programmed at location pa ia = address: 0000h for manufacturing code, 0001h for device code pva = data to be read from location pa at program verify id = id data read from ia during product id operation (manufacturer = 89h, device = b4h) truth table mode description ce n we n oe a0 a9 v pp i/o pins supply current read only not selected h x x x x v pplo high-z standby output disable l h h x x v pplo high-z active read l h l a0 a9 v pplo d out active i.d. (mfr.) l h l l v id v pplo d out =89h active i.d. (device) l h l h v id v pplo d out = b4h active command program not selected h x x x x v pphi high-z standby output disable l h h x x v pphi high-z active read l h l a0 a9 v pphi d out active write l l h a0 a9 v pphi d in active l = low, h = high, x = don?t care 30a072-12 rev. c 3
dpz512x32iv3 dense-pac microsystems, inc. dc operating characteristics: over operating ranges symbol characteristics test conditions limits unit min. max. i in input leakage current v in = 0v to v dd -16 +16 m a i out output leakage current v i/o = 0v to v dd , ce or oe = v ih , or we = v il -40 +40 m a i cc1 operating supply current ce = v il , v in = v il or v ih , i out = 0ma, f = 8mhz 130 ma i cc2 v dd programming current programming in progress 130 ma i cc3 v dd erase current erasure in progress 130 ma i sb1 standby current (ttl) ce = v ih 16 ma i sb2 full standby supply current (cmos) ce = v dd -0.2v 1.6 ma i pps v pp leakage current v pp = v pplo 160 m a i pp1 v pp read current v pp = v pphi 3.2 ma i pp2 v pp programming current v pp = v pphi , programming in progress 125 ma i pp3 v pp erase current v pp = v pphi , erasure in progress 125 ma i id a9 i.d. current a9 = v id , ce = oe = v il , we = v ih 2.0 ma recommended operating range 2 symbol characteristic min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v v pp programming voltage 11.4 12.0 12.6 v v il input low voltage -0.5 3 0.8 v v ih input high voltage 2.0 v dd +0.5 v t a operating temperature c 0 +25 +70 c i -40 +25 +85 m/b -55 +25 +125 v id a9 i.d. input/output 11.5 13.0 v capacitance 7 : t a = 25c, f = 1.0mhz symbol parameter max. unit condition c adr address input 100 pf v in 3 = 0v c ce chip enable 20 c we write enable 50 c oe output enable 100 c i/o data input/output 50 absolute maximum ratings 7 symbol parameter value unit t stc storage temperature -65 to +150 c t bias temperature under bias -55 to +125 c v id voltage on a9 2 -0.5 to +14.0 4, 5 v i out output short circuit current 100 6 ma v i/o input/output voltage 2 -0.5 to +7.0 3 v v pp v pp supply voltage 2 during erase/program -0.5 to +14.0 4 v v dd supply voltage 2 -0.6 to +7.0 4 v dc output characteristics symbol parameter condition min. max. unit v oh high voltage i oh = -2.5ma 2.4 v v ol low voltage i ol =5.8ma 0.45 v 30a072-12 rev. c 4
dense-pac microsystems, inc. dpz512x32iv3 ac test conditions input pulse levels 0v to 3.0v input pulse rise and fall times 5ns input and output timing reference levels 1.5v output timing reference levels during verify 0.8v and +2.4v output load load c l parameters measured 1 100 pf except t df , t lz and t olz 2 30pf t df , t lz and t olz ac operating conditions and characteristics - read cycle: over operating ranges no. symbol parameter 120ns 150ns 170ns 200ns 250ns unit min. max. min. max. min. max. min. max. min. max. 1 t rc read cycle time 120 150 170 200 250 ns 2 t ce chip enable access time 120 150 170 200 250 ns 3 t acc address access time 120 150 170 200 250 ns 4 t oe output enable access time 50 55 60 60 65 ns 5 t lz chip enable to output in low-z 7, 8 0 0 0 0 0 ns 6 t olz output enable to output in low-z 7, 8 0 0 0 0 0 ns 7 t df output disable to output in high-z 7, 8 30 35 40 45 60 ns 8 t oh output hold from address, ce or oe change (whichever occurs first) 0 0 0 0 0 ns ac operating conditions and characteristics - write cycle: over operating ranges no. symbol parameter 120ns 150ns 170ns 200ns 250ns unit min. max. min. max. min. max. min. max. min. max. 9 t wc write cycle time 120 150 170 200 250 ns 10 t as address setup time 0 0 0 0 0 ns 11 t ah address hold time 60 60 60 60 60 ns 12 t ds data setup time 50 50 50 50 50 ns 13 t dh data hold time 10 10 10 10 10 ns 14 t wr write recovery time before read 6 6 6 6 6 m s 15 t rr read recover time before write 0 0 0 0 0 ns 16 t cs chip enable setup time before write 20 20 20 20 20 ns 17 t ch chip enable hold time 0 0 0 0 0 ns 18 t wp write pulse width 9 80 80 80 80 80 ns 19 t wph write pulse width high 9 20 20 20 20 20 ns 20 t dp duration of programming operation 10 10 10 10 10 m s 21 t de duration of erase operation 9.5 10.5 9.5 10.5 9.5 10.5 9.5 10.5 9.5 10.5 ms 22 t vpel v pp setup time to chip enable low 4 1.0 1.0 1.0 1.0 1.0 m s 1.3v 3.3k w 1n914 c l * d out figure 1. output load * including probe and jig capacitance. device under test 30a072-12 rev. c 5
dpz512x32iv3 dense-pac microsystems, inc. read cycle address ce oe we data out 5.0v v dd 0v erase cycle address ce oe we data i/o 5.0v v dd 0v v pph v pp v ppl 30a072-12 rev. c 6
dense-pac microsystems, inc. dpz512x32iv3 programming cycle 9 address ce oe we data i/o 5.0v v dd 0v v pph v pp v ppl alternative write timing ce we notes: 1. each slcc contains two flash memory devices enabled by a common chip enable. typically this module would be used as a x32 device with ce 0 and ce 1 tied together. when writing commands to the command register under these conditions, the command shown in the command definition table should be duplicated to each byte (i/o0 - i/o7, i/o8 - i/o15, i/o16 - i/o23, i/o24 - i/o31) of the module. if the command to be written is 40h like that for setup program/program, 40404040h would be written to the module followed by the 32 bit data. a single device can be programmed or erased by writing the appropriate command to the device the operation is to be performed on while 00h is written to the other devices that are enabled at the same time. care must be taken when doing program verify on a single device. make certain that no other devices are driving the data bus of the devices that are not being verified but are enabled along with the device that is being verified. any device that is enabled during program verify will be driving the data bus with the data that is programmed at that address. 2. all voltages are with respect to v ss . 3. -2.0v min. for pulse width less than 20ns (v il min. = -0.5v at dc level). 4. maximum dc voltage on v pp or a9 may over shoot to +14.0v for periods less than 20ns. 5. output shorted for no more than 1 second. no more than one output shorted at a time. 6. stresses greater than those under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 7. this parameter is guaranteed and not 100% tested. 8. transition is measured at the point of 500mv from steady state voltage. 9. chip enable controlled writes: write operations are driven by the valid combination of chip enable and write enable. in systems where chip enable defines the write pulse width (within a longer write enable timing waveform) all set-up, hold, and inactive write enable times should be measured relative to the chip enable waveform. 30a072-12 rev. c 7
dpz512x32iv3 dense-pac microsystems, inc. figure 2: write algorithm 30a072-12 rev. c 8
dense-pac microsystems, inc. dpz512x32iv3 figure 3: erase algorithm 30a072-12 rev. c 9
dpz512x32iv3 dense-pac microsystems, inc. figure 4: high performance parallel erasure (conceptual device) note: [1] you mask the device by substituting a reset command for the erase and verify commands, that way the erased byte idles through the next erase loop. 30a072-12 rev. c 10
dense-pac microsystems, inc. dpz512x32iv3 figure 5: parallel erase flow chart notes: [1] wait for vpp to stabilize. [2] use quick-pulse programming algorithm. [3] initialize variables: plscnt_hi = high byte pulse counter plscnt_lo = low byte pulse counter flag = erase error flag adrs = address e_com = erase command v_com = verify command [4] erase verify command stops erasure. [5] see figure 6 for subroutine. [6] when both devices at adrs are erased, f_data = ffffh. [7] reset commands to default e_com = 2020h, v_com = a0a0h before verifying next adrs. [8] reset device for read operation. 30a072-12 rev. c 11
dpz512x32iv3 dense-pac microsystems, inc. figure 6: device erase verify and mask subroutine notes: [1] this subroutine masks the high byte or low byte of the erase and verify commands from executing during the next operation. [2] mask the high byte with 00h. [3] if the low byte verifies erasure, then mask the next erase and verify commands with ffh (reset). [4] if the low byte does not verify, increment its pulse counter. [5] check for max. count. flag = 1 denotes a low byte error. [6] repeat sequence for high byte. [7] flag = 2 denotes a high byte error. flag = 3 denotes both high byte and low byte errors. 30a072-12 rev. c 12
dense-pac microsystems, inc. dpz512x32iv3 dense-pac microsystems, inc. 7321 lincoln way u garden grove, california 92841-1428 (714) 898-0007 u (800) 642-4477 (outside ca) u fax: (714) 897-1772 u http://www.dense-pac.com mechanical drawing ordering information 30a072-12 rev. c 13

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